The present invention relates in general to semiconductor processing methods for forming silicide. More particularly, it relates to a method for forming silicide over silicon-containing areas in a semiconductor device and a semiconductor device formed thereby.
As integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. Nevertheless, resistance of a source/drain region in metal oxide semiconductor (MOS) transistors increases, and the polysilicon electrodes that form the MOS gates and wiring lines within semiconductor devices introduce undesirable resistance. To reduce resistance and RC delay time to improve the operating speed of a device, a silicide layer is employed. Thereby, a response time and operating speed of the entire device is increased.
A typical implementation of a silicide layer on a polysilicon electrode or a silicon substrate is known as a self-aligned silicide (salicide) process. Titanium silicide (TiSi2) is commonly used as a salicide material. One problem in forming salicide having line widths less than about 0.5 μm is the tendency of titanium silicide to agglomerate when forming overlying gate, source, and drain regions and subjected to high annealing temperatures, typically using a rapid thermal anneal (RTA). For example, in the formation of titanium silicide, typically a two-step process is required to form the low electrical resistance phase of titanium silicide, frequently requiring annealing temperatures of up to 800° C. In smaller line width areas, the titanium silicide has difficulty achieving the nucleation and growth of the crystalline phase required for low electrical resistance, requiring higher annealing temperatures which frequently causes agglomeration of the silicide. This effect is referred to as the narrow line effect. Cobalt silicide (CoSi2) is a preferred material for forming salicide for sub-quarter micron devices since the required phase transformation to form the low electrical resistance crystalline phase takes place at lower temperatures, for example, from about 700° C. to about 900° C., avoiding silicide agglomeration. Nevertheless, the inventors have encountered problems of poor resistance uniformity over the process wafer when forming cobalt silicide on P-type polysilicon, which sometimes results in out of specification sheet resistance over a large percentage of the silicided wafer area.
An improved method for forming low resistance salicide over sub-quarter micron semiconductor devices with reliable and uniform electrical behavior is thus called for.